The present invention relates to a method and device for designing a semiconductor integrated circuit.
Due to the recent increase of mobile devices, a semiconductor integrated circuit is required to have a large scale while consuming less power. However, due to the scale enlargement of the semiconductor integrated circuit, a plurality of functional blocks is located on the semiconductor integrated circuit, and the power consumption of each functional block has increased.
In addition to the current consumed during operation of the semiconductor integrated circuit, the current consumed when the semiconductor integrated circuit stops functioning, especially, the leakage current produced when the power is off has a tendency of increasing. Originally, the off leakage current of a CMOS transistor, which forms a semiconductor integrated circuit, is small and was thus ignored. However, the higher integration of a semiconductor integrated circuit has resulted in the miniaturization of the CMOS transistor and shortened the gate length. Thus, the off leakage current can no longer be ignored. Accordingly, a semiconductor design tester has been proposed to reduce the off leakage current when designing a semiconductor integrated circuit (for example, Japanese Laid-Open Patent Publication No. 2005-190237).
In the semiconductor design tester described in Japanese Laid-Open Patent Publication No. 2005-190237, the power consumption is calculated from signal level/signal information files, which are obtained by simulating internal signals of a semiconductor integrated circuit, and a technology library file. Based on the value of the calculated power consumption, logic synthesis is performed so that one circuit cancels the off leakage current of another circuit. Accordingly, logic synthesis that is effective for reducing the off leakage current has been automatically performed without manually correcting the gate net list.
However, in the semiconductor design tester described in Japanese Laid-Open Patent Publication No. 2005-190237, to reduce the off leakage current, the power consumption of the semiconductor integrated circuit must be calculated and logic synthesis must be performed. Such processing is complicated and burdensome.